KARTHIKEYAN PERUMAL
14/2, 4th Main Link Road
Present Post Office
Madiwala, Bangalore – 560068
Email : Karthikeyanperumalece AT gmail.com
Mobile : 8608445435
CAREER OBJECTIVE :
To ensure a challenging position in a growing organization in the domain of VLSI Analog layout design and verification, where I would be able to utilize my capabilities to the best extends and in the process adds value to the organization and my career.
TECHNICAL SUMMARY :.
** Comprehensive knowledge of designing Analog circuit and Analog layout design in Cadence Virtuoso a scale of 180 nm.
** Immense ability to create schematics and verification take block through DRC, LVS, Antenna rule checking, parasitic extraction and ERC checks for physical verification.
** Extensive knowledge of designing various layouts by using CMOS standard processes
** Sound knowledge of matching resistors, debugging DRC and managing layout design.
** Intensive self-learning to implemented own CHIP design based on SOC and which published in International Innovative Research Journal of Engineering and Technology.
** Excellent communication skills and has the ability to work independently
ACADEMIC PROFILE :
** 2016 Bachelor of Engineering in Electronics and Communication Engineering CK College of Engineering and Technology, Cuddalore. CGPA - 6.99
** 2013 Diploma in Electronics and Communication Engineering Krishnaswamy Memorial Polytechnic College, Cuddalore - 86.33%
** 2010 SSLC St.Joseph’s higher secondary School- Manjakuppam, Cuddalore - 61.6%
PUBLICATION & CONFERENCE :
** Published journal paper title Performance optimization on a system on chip using I²C concept - 6g computer at International Innovative Research Journal of Engineering and Technology, (IIRJET)Melange publication, volume 1, issue no.04, June 2016.
** Presented paper in isparkz'16 conference Delay optimization in multi-core processor on SOC using I2C at SKP College of engineering and technology, Tiruvannamalai on 2nd April 2016.
EXPERIENCE :
Employer : Venbha HD Entertainment
Experience : July 15, 2016, to Current
Role : Technical Engineer
Description : Have to Work and executed the following Work Nature:
** Involved in Channel Configuration with MSO via AGILE RF Modulator for Frequency Allocation for the Local Channel also get the Loss Free Transmission.
** Involve Guided cabling type and Initialization Technology to get the loss-free transmission.
** Involve in Troubleshooting of Broadcasting Software and Windows if required.
TECHNICAL PROJECT :
BE :
Title : Clock Design Routing Algorithm in Cadence Tool
Description :
** The main objective of the project to design a Clock routing algorithm.
** The design can be done by exciting of clock routing algorithm (such as weighted center, Exact Zero Skew, DME algorithm) which may lead to the flow of clock routing to attain the minimum skew rate.
** It improves the performance of internal clock routing in an IC and performance of execution process with minimum amount of delay
Implementation : The project implemented in Cadence virtuoso scale of 180 nm.
BE:
Title : Performance Measure on System on Chip using I2C Concept
Description :
** The main objective of the project to design a Multi-Core architecture in a SOC Chip.
There are two phases
** The system provides Improves Area performance, Speed, reduction of delay in Single Chip by an I2C concept in which coordinates the various processors in a single die.
** Designed a four different set processor on the single chip, which was asymmetric technique based Multi-core Architecture is used.
** The outcome of Processor terminates control over on external various peripherals such analog and digital devices which oriented by Embedded OS.
Implementation :
The project implemented in Spartan 3E kit and with help of software Xilinx 14.7 ISE Design Suite.
Diploma :
Title : Interactive Voice Response for Industrial Control
Description :
** The main objective of the project to control overall industry equipment by Mobile communication. There are two phases
** The system can update current scenario of Machinery in Industry which controls the equipment by PIC Controller.
** The Status Condition can invite to respective authority via Mobile and controlled remotely to direct command held of DTMF decoder.
Implementation:
The project implemented in PIC Controller kit and with help of software keil micro vision.
MINI PROJECTS :
** Mobile Detector
** Soil Moisture Contro
** Robo Ivory Robot
REWARD & RECOGNITION :
** Won Second prize in the paper presentation on FPGA based Multi-core processor at Shri krishnaa College of engineering & technology, Pondicherry from 10th to 11th February 2016.
** Participated in 3 days value added the course on Cadence tool in VLSI design conducted by cadence Pvt.ltd Bangalore at CK College of engineering and technology, Cuddalore from 28th to 30th January 2015.
** Won Gold Medal in District Level Mega Chess Tournament 2015 organized by Cuddalore Chess Academy on 11th July 2015.
** Appraisal of Certificate of In-Plant training in manufacturing operations at Lenovo (India) private limited, Pondicherry from 11th to 23rd December 2014.
** Participated in workshop on Testing of Electronic Devices at Krishnaswamy Memorial Polytechnic College, Cuddalore on 22nd December 2011.
DECLARATION :
I hereby declare that the details/particulars contained in this document are true and correct to the best of my knowledge.
PLACE :
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