PROFESSIONAL SUMMARY :
Meticulous and analytical researcher with 5 years of educational and hands-on experience in VLSI low power design. Adaptive team player with in -depth knowledge of data collection and problem solving. A highly motivated individual committed to hard work and intensive analysis. Flexible and polished senior Research associate promoting well developed skills in Cadence EDA tool and H-spice simulation tool.
SKILL :
** Cadence EDA tool
** H-Spice simulation tool
** Tanner tool
** Experiment design
WORK HISTORY :
Worked on several projects listed
** “Design and Analysis of CNTFET Based 10T SRAM for high performance at nano scale” Published in International Journal of Circuit Theory and Applications(SCI Indexed Wiley publication Journal)
** “Consequences of body biasing technique on SRAM memory cell” published in International Journal of Innovative Technology and Exploring Engineering(SCOPUS indexed) .
** “Analysis of Body bias impact on the performance parameters of CMOS Inverter” presented in National conference held at NITTTR Chandigarh (SLIETCON-2019).
** “Low Power 3-Bit Flash ADC Design with Leakage Power Reduction at 45 nm Technology” IEEE InternationalConferenceon Information Science and Technology (ICIST 2018) in Spain during June 30-July 6, 2018 [SCOPOUS indexed].
** “Comparative Analysis of Standard 9TSRAM with the Proposed Low-Power 9TSRAM” Springer International conference presented at Jaypee university Noida, published as a chapter in a book titled as Advances in Signal Processing and Communication, Lecture Notes in Electrical Engineering https ://doi.org/10.1007/978-981-13-2553-3_52, 2018 (SCOPUS indexed).
** “Analysis of CMOS based NAND and NOR Gates at 45 nm Technology” International Journal of Electronics, Electrical and Computational System IJEECS ISSN 2348-117X Volume 6, Issue 4, April 2017(UGC APPROVED JOURNAL).
** “Performance evaluation of 6T, 7T & 8T SRAM at 180 nm technology”, 8th International Conference on Computing, Communications and Networking Technologies, ICCCNT, 2017 organized at IIT Delhi (pp. 1–6). doi : 10.1109/ICCCNT.2017.8204092 (SCOPUS indexed).
** “A Novel Approach of standard database generation for defect detection in Bare PCB” has been presented in International conference on computing, communication, and automation organized by IEEE in May 2015 (SCOPUS indexed).
** “Performance of BAA Edge detector on different gray images affected by different kinds of Noise” has been presented in International conference Futuristic trends in computational analysis in knowledge management organized by IEEE student branch in February 2015.
** “PCB Image Enhancement using Machine Vision for effective defect detection” has published in International Journal of Advanced Engineering Research and Science (IJAERS) in August 2014.
WORKSHOP/SHORT TERM COURSE ATTENDED :
** Attended two week workshop on “Python programming” organized by SSDC, SLIET, Longowal during February 09-22, 2020 .
** Attended five days short term course on “Nano-electronics & VLSI : Devices, Circuits, and Systems” organized by ECE department, NIT Uttarakhand in collaboration with SLIET, Longowal during November 04-08, 2019.
** Attended one week Short term training program on “Recent Trends in Electronics and Communication Engineering” organized by ECE department SLIET, Longowalfrom September 24-28, 2018.
** Attended one week Short term training program on “Modelling and Simulation using MATLAB” organized by Electrical and Instrumentation department SLIET, Longowalfrom May 21-25, 2018.
** Attended three days workshop on “Analog CMOS integrated Circuit Design” organized by ECE department SLIET, Longowalfrom April 14-16, 2018.
** Participated in Faculty development programme on “VLSI Devices and Technology” conducted by E&ICT Academy at IIT Roorkeefrom October 3-8, 2017
** Attended two days TEQIP-II Sponsered workshop on “MEMs Systems and Design” organized by ECE department SLIET, Longowalfrom October 24-25, 2016.
** Attended one week Short term training program on “ Frontiers in Electronics and Communication Engineering” organized by ECE department SLIET, Longowalfrom September 19-23, 2016.
** Attended three days workshop on “Simulation and Modelling, organized by Computer Science and Engineering department”, SLIET, Longowalfrom September 8-10, 2016.
** Participated in workshop on VLSI Design flow using Cadence EDA Tool organized by ECE department, SKIT, Jaipurfrom May 25-26, 2016.
** Attended Short term training program on “Renewable energy applications : Practices and Challenges” at SLIET, Longowalfrom December 21-25, 2015.
** Attended one week Short term course on “Computer vision and pattern recognition” organized by Information Technology department, NIT Durgapurfrom June 16-20, 2014.
** Attended National workshop on “Biometrics and privacy protection” organized by Computer Engineering department, MNIT Jaipurfrom December 23-25, 2013.
** Attended two week winter school on “Future trends of broadband wireless communications and networking” organized by ECE department, SLIET, Longowalfrom December 9-20, 2013.
EDUCATION :
** PhD (VLSI technology and design) (About to completion)
** Sant Longowal Institute of Engineering Technology, Longowal , Sangrur, Punjab
** M.Tech, 06/2014 Sant Longowal Institute of Engineering Technology, Longowal , Sangrur, Punjab
** B.Tech, 07/2011 Techno India College of Technology, WBUT, Kolkata
** Intermediate, 07/2001 G.
D. College, Begusarai, Bihar
** Matriculation, 06/1999 B. S. S. Inter Collegiate School, Begusarai, Bihar
CERTIFICATION :
** Qualified GATE Exam two times in 2011 ( grab scholarship during M.Tech ) and 2019
** UGC NET also qualified for two times in December 2013 and June 2014.
** Working as a reviewer in peer reviewed SCI/ SCIE journals like International Journal of Circuit Theory & Applications, and Semiconductor Science & Technology
EXPERIENCE :
Senior lecturer (08/2014 – 07/2015)
Jaipur engineering College and Research Center, Jaipur, Rajasthan
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