GAUTAM KUMAR
Email : gautam.iimtgn AT gmail.com
CAREER OBJECTIVE :
To obtain a position in an industry that gives an opportunity to explore, develop and utilize technical skills involved in various stages of Electronics hardware development life cycle and to gain experience and domain knowledge.
PROFESSIONAL EXPERIENCE :
** Currently working as Design and Verification Intern AT SION Semiconductor from jul-9-2018 till date
** 1 year of experience at SION Semiconductor pvt ltd (+ previous 6 months of experience at JB tech India in asic design.)
** Design and verification of asynchronous FIFO using System Verilog.
** Worked on FPGA Spartan 6
** Design of low power sequential circuit design of ALU and its implementation on FPGA.
Implemented verification methodologies, assertions, code coverage, functional verification and created test benches for different DUT.
SKILLS :
Programming language : Verilog,System verilog, UVM, C
Scripting language : Shell
Software Skills : Xilinx, Modelsim, Questasim, Multisim, Arduino IDE, Keil, Proteus, Eagle, Mat lab Protocols : UART, SPI, I2C
Hardware Skills : Xilinx Spartan 3e, Embedded (Avr and Arm)
Operating systems : Windows, Linux
Languages Known : English and Hindi
PROJECTS :
Universal Asynchronous Receiver Transmitter (UART). Designed, Verified & Synthesized a UART protocol. The whole code is written in the Questasim software using System Verilog language and is verified using directed test benches. After Synthesis, design was implemented on Spartan 3E Xilinx Kit.
Language : System Verilog
Tools Used : Questasim
Design and Functional verification of Asynchronous FIFO using SV :
This project included the design and functional verification of Asynchronous fifo. I created a complete verification environment using SV which comprised of creation of all the classes like transaction, generator, driver, monitor, scoreboard, environment and top.
Methodology : System Verilog
Tool used : Questasim
Company : SION Semiconductor Pvt.
Ltd.
Serial Peripheral Interface (SPI) :
Designed, Verified & Synthesized a SPI protocol. The whole code is written in the Questasimsoftware using System Verilog language and is verified using directed test benches. After Synthesis, design was implemented on Spartan 3E Xilinx Kit.
Tools Used : Questasim
Language : System Verilog
Design of one way traffic light controller and its implementation on FPGA :
The normal function of traffic lights required more slightly control and coordination to ensure that traffic moves as smoothly and safely as possible and that pedestrians are protected when they cross the roads.In this project I coded RTL code for the design using verilog and implemented its design to xillinx FPGA kit to verify it.
Language used : Verilog.
Tools : Xillinx ISE Design tool.
Company : JB Tech India.
ACADEMIC QUALIFICATIONS :
1. HSC, Jesus and merry academy Common subs. 78 2011
2. SSC, N.D.J College PCM 68.4 2013
3. B.TECH , IIMT E.C.E 62.46 2018
INTEREST AREAS :
** Areas related to SoC, communication protocol design/verification.
** FPGA/ASIC design and verification domains.
** Research domains in Digital communication, microprocessors.
STRENGTHS :
** Self-motivation and ability to take the initiative.
** Ability to work well under pressure.
** Quick learner, keen to learn and improves skills.
** Team planner and good in motivating others.
** Willing to work and adopt to new opportunities and challenges
HOBBIES & INTEREST :
Reading novels, Listening to Music, Playing guitar
PERSONAL INFORMATION :
Date of Birth : 20th July 1996
Father’s Name :Mr.SHASHIDHAR MALLICK
DECLARATION :
I hereby declare that the information furnished above is true to the best of my Knowledge and belief.
PLACE : Bangalore
DATE :