VIKRANT VASHISHTHA
Mobile Number : 8920233134
Email : vashishthavikrant AT gmail.com
CAREER OBJECTIVE :-
Seeking a technical position in Semiconductor Company thatwill utilize and enhance my skill sets in the field of IC design.
SUMMARY :-
** Good understanding of the ASIC design flow.
** Understanding of net list to GDSII flow.
** Good understanding of physical design concepts.
** Working knowledge in PERL scripting.
** Hands on experience of industry standard cadence EDA tools.
** PnR tool : Cadence Encounter
** Basic fundamentals knowledge of CMOS
** Fundamental knowledge of Digital design.
** Fundamental knowledge of STA
PROFFESIONAL TRAININGS :-
I am involved in six months Industrial Training of Physical Design at Pine training Academy, Ghaziabad.
Synopsis of Training :-
** Familiarity with LINUX platform.
** Understanding of ASIC design flow overview.
** Understanding of Physical Design flow.
** Exposure of industry standard EDA tool Cadence Encounter.
** Good understanding and Practical Exposure of Physical Design concepts.
PROJECT 1 :-
** Project –Block Level
** Objective – To make a good and congestion free floorplan with minimum usage of die size.
** Technology/Layers – 90nm /9 layers
** Standard cells/Macros – 29 macros/18K
** Tool used - Cadence Encounter.
Steps Involved :-
** Die size and core size estimation
** Finding Design utilization and Aspect Ratio
** Macro placement
** Channel allocation between Macros.
** Adding of Halo and soft blockages and density screen
** Floorplan Sanity checks performed
** Power planning for block.
** Creation of Power rings around the Core
** Making of power mesh inside the core
** Created dedicated power rings around Analog IP’s
Challenges faced during Project :-
Notches formed in the floor plan.
PROJECT 2 :
** Objective – To perform Placement, CTS and Routing of the design.
** Technology/Layers – 90nm/9 layers.
** Standard cells/Macros – 4 macros/35K.
** Description - Block includes 4 macros, 35k standard cells with supply voltage of
** 1.8v, working at operating frequency of 250 MHz. It has total of 3 clocks (2 propagated and 1 generated), 9 metal layers are used and in this project we done placement, clock tree synthesis, routing .
** Tool used - Cadence Encounter.
Roles :-
** Perform checks on input database before proceed to next step.
** Run Congestion driven placement and optimization.
** Prepare placement bounds for timing critical modules.
** Define NDR rules before CTS run.
** Define metal layers used for clock nets
** Define clock buffer/inverter, clock gates for CTS creation.
** CTS done in full mode to find skew as well as balancing of the clock tree.
** Run setup and hold timing optimization post CTS.
** Routing of the design.
Challenges :-
** Analysis of Congestion and hotspot after placement.
** Improve congestion by applying various blockages (i.e.
hard, soft, and partial).
** Meet hold timing requirements after CTS.
** Interpreted various timing reports
INDUSTRIALTRAININGS :-
** Summer Training atXperia Technologies Pvt Ltd Nirman vihar, New Delhi-Training was based on to gain basic knowledge of microcontroller (8051), it's programming and explore various applications of embedded systems in technical fields.
** ALL INDIA RADIO, Prasar BHARATI, New Delhi-Training was based on to understand each step comes in the transmissionprocess of radio program from originating station to common FM receiver.
ACADEMIC QUALIFICATIONS :-
** B.Tech Inderprastha Engineering College AKTU 2017 63.94%
** 12th Joseph and Mary Public School CBSE 2013 77.3%
** 10th Joseph and Mary Public School CBSE 2011 81.7%
ACADEMIC PROJECTS :-
** Water ATM using RF ID-Main objective of project is to provide water in metro premises which is not available yet at reasonable prices and person will drink as much as he/ she want and make payment using their metro card there is no need to carry change.
** Home automation system using Bluetooth- Main motive of project is to create a communication link between our Smartphone’s and electrical switch boards. Bluetooth technology is pretty economical and household items comfortably covered with in Bluetooth transmission.
PERSONAL INFORMATION :-
Full Name: Vikrant Vashishtha
Fathers Name: Dinesh Kumar Sharma
Date of Birth :April 8 , 1996
Nationality: Indian
Address :k-86 street no. 20A ,Bhajanpura , New Delhi
Pincode :110053
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