Magesh. E
Email : magesh.e001 AT gmail.com
Mobile : (+91) 9489958255
CAREER OBJECTIVE :
To work for a professional organization which offers challenging opportunities and excellent cooperative working environment to utilize my technical and professional knowledge, enabling me to improve my abilities, develop my functionality and improve the organization work plans and procedures.
ACADEMIC CREDINTIALS :
1. M.E. Applied Electronics C.S.I Institute of Technology, Kanyakumari 7.71 2014-2016
2. B.E. Electronics and Communication Engineering Marthandam College of Engineering and Technology, Kanyakumari 6.78 2010-2014
3. Higher Secondary Certificate (HSC) D.V.D Higher Secondary School, Kanyakumari 72% 2010
4. Secondary School Leaving Certificate (SSLC) Carmel Higher Secondary School, Kanyakumari 84% 2008
CERTIFICATION :
Cisco Certified Network Associate (CCNA) v3.0 200 -125 Certified.
Cisco ID : CSCO13118078
TECHNICAL SKILLS :
CCNA :
** IP Addressing & Sub netting.
** Configuring and maintaining routers and switches.
** Configuring VLAN’s, VTP and STP in switches.
** Configuring and troubleshooting RIP, OSPF and EIGRP in routers.
** Routing method’s Static routing, Default routing and Dynamic Routing.
Hardware & Networking Essential Skills :
** Assembling & Dissembling of computer.
** Installation of operating system from windows XP to windows 10.
** Configuration of network & troubleshooting.
** IP addressing.
** Local area network basics.
Operating System Knowledge :
** Installation of win XP, win 7, win 8, win 2003, win 2008, and win server 2012.
** Managing local user and groups, files and folders, desktop settings.
** Working with disk management, backup and restoring data.
PROJECT WORK :
Title : A Class of SEC-DED-DAEC Codes Derived From OLS Codes and Decoded with Low Latency
Project Type : Major PG Academic Project
Organization : C.S.I Institute of Technology, Kanyakumari
Tenure : January 2016 to April 2016
Description : Error correction and detection in a bit by using Double Adjacent Error Correction (DAEC) Code to reduce decoder complexity and delay.
Title : Test Patterns of MSIC Vectors in BIST Scheme
Project Type : Major UG Academic Project
Organization : Marthandam College of Engineering and Technology, Kanyakumari
Tenure : January 2014 to April 2014
Description : Provide generation of Multiple Single Input Change (MSIC) test patterns to make the BIST Scheme faster with low power consumption.
In my project only one bit gets change for each scan chain which reduces the power consumption and achieves high fault coverage.
ACADEMIC ACHIEVEMENTS :
Paper Published in “International Journal of Scientific and Engineering Research (IJSER)” Volume 7,Issue 4, April 2016 ISSN 2229-5518
Paper Number : I080304
Paper Title : A Class of SEC-DED-DAEC Codes Derived From OLS Codes and Decoded with
LOW LATENCY :
** Attended a short term Inplant Training Program in “Fundamentals of Telecom”, Organized by BSNL, Nagercoil.
** Paper Presented a titled “A Class of SEC-DED-DAEC Codes Derived From OLS Codes and Decoded with Low Latency” in IEEE Sponsored Online International Conference on Green Engineering & Technologies by the Department of ECE (PG), Karpagam College of Engineering, Coimbatore.
** Paper Presented a titled “A Class of SEC-DED-DAEC Codes Derived From OLS Codes and Decoded with Low Latency” in National Conference on Advanced Communication & Electronic Systems(NCACES’16) held at Rohini College of Engineering and Technology, Kanyakumari.
PERSONAL DETAILS :
Father’s Name : K. Essakimuthu
Mother’s Name : S. Sreekala
Date of Birth : 17th December 1992
Gender : Male
Nationality : Indian
Languages known : English, Tamil
Permanent Address : 297, DVD Colony,
Kottar, Nagercoil,
Kanyakumari -629002.
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