Biodata |
|
| Name of the Candidate | : | [Private] |
| Name of the Post Applied | : | Engineering Lecturer |
| Job related skills / software | : | Verilog, Assembly Programming, MATLAB, ALTERA FPGA, VHDL, EDA Tools ALTERA Quartus, P-Spice |
| Category | : | Teaching Lecturer Faculty |
| Sub Category | : | Lecturer |
| Years of Experience | : | 0 years |
| State | : | Kerala |
| Gender | : | Female |
| Salary Expected per Month(Rs) | : | 15,000 to 20,000 |
| Highest Qualification attained | : | B.Tech. : Bachelor of Technology |
| Major / Specialization | : | Electronics & Communication |
| Email Id | : | [Private] |
| |
| Are you looking for job now? | : | Yes |
| Can the recruiter contact you? | : | Yes |
|
Sponsored Links:
|
Resume Format / CV Sample Template / Example / Model : |
|
Carrier Objective :
To become part of the organization where I can contribute my skills for organization's growth to explore my knowledge for the improvement of students and good result of the college.
Educational Profile :
Course Year of study Board/ University Institution Percentage of Marks
S.S.L.C 2005 Kerala St.Antony's H S Vandanmedu. 88%
Plus Two 2007 Kerala St.George's Higher Secondary School, Kattappana. 87%
B. Tech in Electronics & Communication Engineering 2007-2011 Mahatma Gandhi University, Kottayam, Kerala. Mar Baselios College of Engineering and technology Peermade. 76%
M. Tech in VLSI and Embedded Systems (Pursuing 4th Semester) 2013-2015 Mahatma Gandhi University, Kottayam, Kerala. Christ Knowledge city, Mannoor. First Semester CGPA Score : 8.52
Technical Skills :
** EDA Tools ALTERA Quartus II, P-Spice o Hardware Description Languages Verilog, VHDL o Software Skills Basics of C, C++, .NET
** Assembly Programming P 8085, C 8051.
** Mathematical Tools MATLAB
** Hardware Expertise ALTERA FPGA
CURRENTLY PURSUING COURSE Doing MTech in VLSI and Embedded Systems Engineering in Christ Knowledge City Mannoor.
Seminar :
I have taken seminar on
1.
Design of Testable Reversible Sequential Circuits.
2. Four-Bit Noninterleaved Data Converter Pair With Built-In Eye Diagram Testability.
Project :
** I completed my mini project on Compression of Encrypted Images in Prediction Error Domain
** In this I done compression of encrypted images in prediction error domain followed by random permutation.
** It is based on prediction of pixel values using context model.
** Comparing to conventional system security and compression efficiency is better.
** This is done in Verilog HDL.
** My main project is VLSI Implementation of Wavelet Based ETC System .
** The basic idea is to improve compression efficiency by using Wavelet transform.
** As the number of zeros increases compression efficiency can be improved.
** Also, decrypt the image that is encrypted and compressed.
Professional Achievements :
** Organized a National conference on NATCOM 2k14 and presented a paper named Design of testable sequential circuits in Qunatum Cell Automata.
** Organized a Workshop, AWOVES to familiarize VLSI tools.
** Organized an International conference on ICCEECON 2k15 and presented a paper named
** Compression of Encrypted Images In Prediction Error Domain
Date :
Place :
|
|
Notes |
|
1. This is an online resume, managed by the candidate.
2. Create your online resume here.
3. If candidate allows, recruiters can contact the candidate directly.
4. Personal and contact details can be kept private optionally by the candidate.
5. Create a link to this online resume where ever you want in the web.
|
|