Biodata |
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| Name of the Candidate | : | Ashwini Burra |
| Name of the Post Applied | : | ASIC/SOC Verification Engineer |
| Job related skills / software | : | Basics of C, Verilog, SV, UVM, AMBA Protocols, MATLAB, Display Serial Interface |
| Category | : | Design Engineering |
| Sub Category | : | Electronics Design/ VLSI Engineer |
| Years of Experience | : | 0 years |
| State | : | Telangana |
| Gender | : | Female |
| Salary Expected per Month(Rs) | : | Negotiable |
| Highest Qualification attained | : | M.Tech. : Master of Technology |
| Major / Specialization | : | Power Electronics and Electrical Drives |
| Email Id | : | ashwiniellaboina AT gmail.com |
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| Are you looking for job now? | : | Yes |
| Can the recruiter contact you? | : | Yes |
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RESUME:
ASHWINI BURRA :
Email :ashwiniellaboina AT gmail.com
CAREER OBJECTIVE:
To obtain a position as a VLSI Design Verification Engineer that will allows me to utilize my strong technical skills, educational background, and ability to work well with the renowned organization, to learn and contribute towards the growth of the organization.
ACADEMICS QUALIFICATION:
** M.Tech Power Electronics and Electrical Drives G. Narayanamma Institute of Technology and Science for Women J.N.T. U 2023 89%
** B.Tech Electrical and Electronics Engineering SR Institute of Technology for women J.N.T. U 2014 78%
** Intermediate MPC Triveni Junior College Board of Intermediate A. P 2010 83%
** SSC Sadhana High School S.S.C 2008 82%
KNOWLEDGE IN SOFTWARE:
Operating Systems : Windows 10, Windows XP, Windows 7.
Software Packages : Ms.Office, basics of C.
TECHNICAL EXPOSURE:
** Knowledge in modelsim MATLAB.
** Good programming skills in System Verilog and Verilog.
** Good understanding and programming skills in verification methodology UVM.
** Good knowledge in AMBA protocol (APB, AHB & AXI).
** Strong technical, logical skills as well as excellent interpersonal skill.
M.TECH - PROJECT DETAILS :
Major P
roject : : MIPI DSI at IP level
HVL : System Verilog.
TB Methodology : UVM
EDA Tools : Riviera Pro – Aldec
Description :
** DSI stands for Display Serial Interface.
** Coded display controller agent to provide timing information and data to MIPI DSI.
** Integrated AHB master agent to configure the MIPI DSI registers to operate in video mode.
** Design supports 1 to 4 lanes and various resolutions.
** Created test plan to cover all features as per specification.
** Coded all AHB sequence to verify all resolutions.
** Pixel data captured in the display controller agent and sent to scoreboard for reference data.
Mini Project :AHB2APB Bridge IP Core Verification
HVL : System Verilog.
TB Methodology : UVM
EDA Tools : Riviera Pro – Aldec
Description : The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.
PERSONAL PROFILE:
Nationality : INDIAN
Marital status : married
Languages Known : Telugu, English, Hindi
DECLARATION:
I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned.
DATE :
PLACE :
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