AdedicatedAdvancedVLSIdesignandVerificationtraineeatMavenSiliconwithabilitytomultitaskandworkwellwithothers. AsaFresheractivelylookingfortheopportunitytoenhancemyprofessionalskillsandcontributestowardsgrowthoftheOrganization.
|
Degree
|
NameofInstitution
|
YearofPassing
|
CGPA
|
|
BTECHinElectronicsandcommunication
|
MVGRCollegeofEngineering
|
2023
|
9.03
|
|
H.S.C
|
NarayanaJuniorCollege
|
2019
|
9.82
|
|
S.S.C
|
SriGuruDuttaEMHighSchool
|
2017
|
9.8
|
HDL : Verilog.
HVL : SystemVerilog.
TBMethodology : UVM.
Protocols : AXI,AHB,UART,I2C,SPI.
Domain : ASIC/FPGAfront-endDesignandVerification.
EDATool : ModelSim,SynopsysDesignCompiler,Cadence Virtuoso,MentorGraphics- QuestasimandXlinix-ISE,Xilinx-Vivado.
ProgrammingLanguages
: C(Datatype, Array, Pointers,MemoryAllocation,List,Queuesandstacks,Data structure,Functions)and
Python
Verification : ConstraintRandomCoverageDrivenVerification,AssertionBased Verification-SVA.
OS : WorkingKnowledgeonWindows,LinuxandCentOS.
Scripting : PerlScripting.
CoreSkills : RTL Coding using Synthesizable constructs of Verilog, FSM-based design, Simulation, CMOSFundamen-tals,CodeCoverage,FunctionalCoverage,Synthesis,StaticTimingAnalysis,AssertionBasedVerifica-tionusingSystemVerilog Assertions.
ToolsusedinEngineering
MATLAB :DigitalSignalProcessing
KeilMDKorArduinoIDE :MicrocontrollerProgramming
MASMorTASM :Assembly Language Programming (8085 or 8086) etcLTSpice(SpiceSimulator) :Circuit analysis
NS2 :Network Simulator for Wireless communication.CadenceVirtuoso :Custom IC design and package/PCB design/analysisSubjectExpertise
Digital electronics, Analog electronic, Network analysis, Analog & Digital Communications, Signals & System, Signal Processing,Microprocessors/Microcontrollers, ComputerOrganization, Wirelesscommunication
DigitalDesign :CombinationalCircuits,SequentialCircuits,FSM,Memories,CMOS DigitalDesignandStandardcells.
STA :STA Basics, STA vs DTA, Timing Path and Constraints, Different types of clocks Clock domain andVariations,ClockDistributionNetworks,Fixingtimingfailure,On-shipvariation,Pessimismremoval.
Verilog :DataTypes,Operators,Processes,BlockingandNon-BlockingAssignments,FSMCoding,LoopingandBranching Construct, System Tasks, Compiler Directives, Block Statements, Pipelining RTL and Test-benchCoding.
Advance Verilog:Generate block, Continuous Procedural Assignments, Self-checking testbench, Automatic Tasks NamedEventsandStratified EventQueue.
Code Coverage : Statementandbranchcoverage,ConditionandExpressionCoverage,ToggleandFSMCoverage.
SystemVerilogHVL
Memories :Dynamicarray,Queue,Associativearray,TaskandFunction-Passbyreference.
Interface : Modportandclockingblock.
Basicandadvancedobject : orientedprogramming-Handleassignments,Copyingtheobjectcontents,
Inheritance,polymorphism,staticpropertiesandmethods,virtualclassesandparameterized classes.
ConstraintRandomization : constraint overriding and inheritance, Distribution and conditional constraints,Soft,staticandinlineconstraints.
Thread synchronizationtechniques: events,semaphoresandMailbox-built-inmethods.
Functionalcoverage : Covergroups,binsandcross-coverage,CRCDVandregressiontesting.
Interfaceandclockingblock,InheritanceandPolymorphism,Constraintrandomization-Inline,distribution,conditional,softandstaticconstraints.Mailboxandsemaphores,Functionalcoverage,CRCDVandregressiontesting.
SystemVerilogAssertions
Typesofassertions,assertionbuildingblocks,sequenceswithedgedefinitionsandlogicalrelationship.Sequenceswithdifferenttimingrelationships.
clock definitions, implication and repetition operators, different sequence compositions, inline and binding assertions,advancedSVAFeaturesandassertionCoverage.
UVM
UVMObjectsandComponents.
UVMFactoryandoverridingmethods.StimulusModelling.
UVMPhases.
UVM Configuration.TLM.
UVMSequence,virtualsequenceandsequencer.IntroductiontoRAL.
1)1x3RouterRTLdesignandVerification
HDL :Verilog
HVL :SystemVerilog
TBMethodology :UVM
EDATools :QuestasimandISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels,channel0,channel1 andchannel2.
Responsibilities:
Architectedtheblocklevelstructureforthedesign.ImplementedRTLusingVerilogHDL.
Architected theclass basedverificationenvironmentusingSystemVerilog.VerifiedtheRTLmodelusingSystemVerilog.
Verifiedthe RTLmodelusingSystemVerilog.Generatedfunctionalandcode coveragefortheRTLverificationsign-off.Synthesizedthedesign.
2)DESIGN OF LOW POWER PARALLEL ARCHITECTURE FOR LFSRs
Mentor : Dr.
Sudhanshu Sekhar Behra
Team Size : 4 Jan 1, 2023 – May 6, 2023
Tools: Vivado
Key Skills:Verilog,FPGA
In this we had used Parallel architecture SIPO model to reduce the power conception of the circuit. With the help of
Vivado Xilinx tool compiled and , simulated and synthesized the RTL code inorder to generate Gate Level Netlist.
Compared the results between basic LFSR Architecture and LFSR by using Parallel Architecture. Also tried to
implement on FPGA Board
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PublishedaJournalatIJRPRonEnhancementofLandingsafetyforAutonomousAerial VehicleusingLiderSensors.
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ParticipatedinDistrictlevelKuchipudi(Classicaldance)competitions.
IYaminiChinthapalli,herebydeclarethatallthedetailsprovidedabovearetruetothebestofmyknowledgeandbelief.
Place: Vizianagaram YaminiChinthapalli