Biodata |
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| Name of the Candidate | : | [Private] |
| Name of the Post Applied | : | VLSI Designer |
| Job related skills / software | : | Verilog and VHDL, PERL and TCL, ModelSim and NC-Sim, Cadence virtuoso, TINA TI, RTL Compiler, SOC Encounter |
| Category | : | Design Engineering |
| Sub Category | : | Electronics Design/ VLSI Engineer |
| Years of Experience | : | 0 years |
| State | : | Andhra Pradesh |
| Gender | : | Male |
| Salary Expected per Month(Rs) | : | 20,000 to 25,000 |
| Highest Qualification attained | : | M.Tech. : Master of Technology |
| Major / Specialization | : | VLSI Design |
| Email Id | : | [Private] |
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| Are you looking for job now? | : | Yes |
| Can the recruiter contact you? | : | Yes |
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P.Venkataramana
D.no :3-226
Karanamgari thota
Gollaprolu Town
East Godavari dist
Andhra Pradesh-533445
E-mail : parvathavenkataramana AT yahoo.in
Alternate e-mail : pvramana4210 AT gmail.com
Contact : +919494775989
CARRIER OBECTIVE :
To work in an environment where I can apply and enhance my knowledge and skill to serve the firm to the best of my efforts.
ACADEMIC QUALIFICATIONS :
M.Tech (VLSI Design) V.I.T University, Vellore. V.I.T University Pursuing (2015) 8.66 CGPA (till date)
B.Tech (E.C.E) M.V.G.R College of Engineering, Vizianagaram. JNTUK 2012 77.67%
Diploma (E.C.E) Govt. Polytechnic, Narsipatnam. S.B.T.E.T 2009 74.78%
Xth class ZP High school, Gollaprolu. SSC 2006 85.16%
TECHNICAL SKILLS :
** Operating systems : Windows and LINUX.
** Computer Language : C.
** HDL Languages : Verilog and VHDL.
** Scripting Languages : PERL and TCL.
** Simulation Tools : ModelSim and NC-Sim.
** Schematic Design : Cadence virtuoso, TINA TI.
** Synthesis : RTL Compiler.
** Physical design : SOC Encounter
PROJETS :
** Design and ASIC implementation of Universal Asynchronous Receiver Transmitter.
** Design and implementation of signal
generator using AT89S52 micro controller with fixed frequency.
** Design and implementation of energy recovery d-flipflop.
Mini projects :
** Design and FPGA implementation of single precision floating point co-processor.
** Verilog coding for BZ-FAD Multiplier for low-power low-area.
** Design of various Analog circuits in TINA-TI.
** Development of verification environment for FIFO controller.
ACADEMIC ACHIEVEMENTS :
** Got 1st prize, in HARDWARE EXPO during my UG, conducted by SPACE, MVGRCE.
** Received Merit Certificate and Scholarship for academic performance in M.Tech 1stsemister.
EXTRA CURRICULAR ACTIVITIES :
** Participated in “BADI BATA”, organized by government of Andhra Pradesh, held in school.
** Organizer and Volunteer in “HINDU E-PLUS”.
** Acted in a short film “ON THE WAY TO SUCCESS” as a part of English project.
PERSONAL PROFILE :
Name : P.Venkataramana
Father’s Name : P.KondalaRao
Gender : Male
Date of Birth and Age : 06th July, 1991; 23 years
Marital Status : Unmarried
Languages Known : English, Telugu
Hobbies : Cricket, listening to music.
DECLARATION :
I honestly declare that the information furnished above is true to the best of my knowledge.
Date : 02.04.2015
Place : Vellore
(P.V.Ramana)
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